The invention relates to a method for checking the functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. The memory addresses of the chip can be selected by address lines electrically biased in a specific manner.
Methods of this type are used in the event of failure of individual memory chips on a memory module, for example a dual inline memory module (DIMM), in order to locate the cause of the failure. Usually responsible for the failure of a memory chip which cannot be properly read from or written to are ruptured soldered connections between the memory chip and the printed circuit board of the memory module.
Until now, the cause has been traced by visual inspection of the existing soldered joints of the address pin contacts. Alternatively, pin contacts selected on a sample basis and suspected of having a ruptured contact connection to the assigned address line of the printed circuit board are re-soldered.
Both methods are time-consuming and only conditionally reliable.
In principle, interrupted electrical connections between the address lines of the printed circuit board and the address line contacts of a semiconductor memory chip can also be traced electrically, in that voltage drops under a constant current are measured or currents under applied voltages are measured. In the case of memory modules with a number of memory chips, for example 8 or 16, the address line contacts of which are connected in parallel by the connected address lines, such tests do not work. Since each address line is connected to each of the memory chips via a pin contact, the created test circuit is closed even when the contact to one of the memory chips is interrupted, by the functioning contact connections to the other memory chips, whereby faultless functioning is indicated in spite of ruptured solder contacts.
It is accordingly an object of the invention to provide a method of checking electrical connections between a memory module and a semiconductor memory chip that overcomes the above-mentioned disadvantages of the prior art methods of this general type, which is more reliable and less time-consuming and which works irrespective of the number of semiconductor chips mounted on the printed circuit board.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for checking a functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Memory cells of the integrated semiconductor memory chip being selected by the address lines being electrically biased in a specific manner. The method includes checking the functional capability of the electrical connections by accessing the integrated semiconductor memory chip through writing and reading operations. The accessing step includes the steps of:
a) writing a first item of information to a first memory cell selected by none of the address lines being electrically biased;
b) writing a second item of information differing from the first item of information to a second memory cell selected by electrically biasing only a single address line;
c) reading from the integrated semiconductor memory chip with the first memory cell being selected by none of the address lines being electrically biased; and
d) checking whether the first item of information or the second item of information was read out.
A sequence of the steps a) to d) is then repeated a number of times and, with each repetition of the sequence of the steps a) to d), a different one of the address lines being electrically biased as the single address line during step b).
According to the invention, a specifically constructed memory test is used instead of an electrical resistance measurement to identify interrupted soldered connections. The invention is based on considerations as to how a semiconductor chip with partly damaged solder contacts reacts when writing and reading operations are initiated. In the case of defective solder contacts, they do not produce usable results in normal memory operation, but are used according to the invention to identify interrupted contact connections.
In a memory module, the memory addresses (cells) of a semiconductor memory chip are selected via address lines which can be electrically biased individually, independently of one another, and as a result, route a binary-coded address to that memory cell which is to be selected in a writing or reading operation. The address lines are connected to pin contacts of the semiconductor memory chip, which has in addition further pin contacts for control lines, data lines or clock lines. The data lines are used for transporting the data to be stored or to be read; the control lines and clock lines serve for making the memory chip operate properly. The address lines are used for transmitting the memory addresses into which the items of memory information transmitted by the data lines are written or from which they are read.
The invention is based in particular on the idea that, if one or more solder contacts are damaged, even though the memory address to be selected is no longer selected, a different memory address is accessed instead. The invention makes use of the fact that, in the event of a defective solder contact, an electrical biasing voltage that is applied to the address line concerned cannot be passed on. Since the electrical potential of the assigned pin contact of the memory chip is xe2x80x9cfloatingxe2x80x9d, the semiconductor chip registers with great probability a grounded address line, whereby, in conjunction with the voltage values of the remaining address lines, a different memory address than the one desired is selected. In normal memory operation, this perception is of no further assistance, since it is unknown which of the usually 14 address line contacts is defective.
According to the invention, however, use is made of the fact that in the semiconductor memory chip there is a single memory address which is always selected if the solder contacts of all the address lines or at least of all the electrically biased address lines are interrupted. The binary digit of this memory address is exclusively made up of xe2x80x9c0xe2x80x9d digital bits. Access to this memory address is used according to the invention to test the contact of a specific address line.
According to the invention, in step a), a first item of information, for example a digital xe2x80x9c1xe2x80x9d, is written into the memory address by none of the address lines being electrically biased. This makes use of the fact that, in the event of interrupted solder contacts, the corresponding contact pins of the memory chip are at a floating potential and consequently are with great probability grounded, so that even in the event of defective solder contacts precisely this memory address is selected. In step b), a different second item of information, for example a digital xe2x80x9c0xe2x80x9d, is written, the memory address now to be selected being selected by only a single address line being electrically biased. Subsequently, in step c), the first memory address is again selected and read from. In step d), it is checked whether this involved reading the item of information stored in step a) or the item of information stored in step b).
If the address line contact to be checked is working, in step b) the different second item of information is written into a different memory address than in step a). In step c), the first item of information stored in step a) is then read out again. If the contact to be checked is interrupted, however, in step b) the second memory address to be selected cannot be selected. Instead of this, since the pin contact does not register an electrical biasing voltage, the second item of information is likewise written into the first memory address. The item of information written in step a) is therefore overwritten in step b) by the second item of information, which is read out in step c). This unexpected memory value indicates a defect of the checked contact connection.
In this way, defective solder contacts can be located by operating the memory on a test basis. The series of steps a) to d) is repeated a number of times, and with each repetition a different address line is electrically biased as the single address line during steps b) and c).
With the foregoing and other objects in view there is further provided, in accordance with the invention, a method for checking a functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Memory cells of the integrated semiconductor memory chip being selected by the address lines being electrically biased in a specific manner. The method includes checking the functional capability of the electrical connections by accessing the integrated semiconductor memory chip through writing and reading operations. The accessing step includes:
a) writing a first item of information to a first memory cell selected by only a single address line being electrically biased;
b) writing a second item of information, differing from the first item of information, to a second memory cell selected by none of the address lines being electrically biased;
c) executing a read command, a same address line as in step a) being electrically biased as the single address line; and
d) checking whether the first item of information or the second item of information was read out.
A sequence of the steps a) to d) is repeated a number of times and, with each repetition of the sequence of the steps a) to d), a different address line being electrically biased as the single address line during step a).
In the case of this method, in step a) the memory address which requires electrical biasing of the address line concerned is selected first. In step b), on the other hand, writing takes place to the memory address selected with address lines at ground potential. In step c), the address selected in step a) is in turn accessed. Depending on whether or not the pin contact of the address line to be tested is connected, in steps a) and c) the address from step b) is actually selected instead of the address to be selected.
If the address line contact is working, in step a) the first item of information, for example a digital xe2x80x9c1xe2x80x9d, is written into the first address to be selected. In step c), which in turn successfully accesses this address, this item of information is read out again. The writing operation in step b) in this case has no effect.
If, however, the address line contact is interrupted, in steps a) and c) the second memory address from step b), which does not depend on electrical biasing, is selected instead of the first memory address to be selected, which depends on electrical biasing. Then, in step a), the first item of information is written into this second memory address; in step b), this item of information is overwritten by the different second item of information, which is subsequently read out in step c) instead of the expected first item of information.
Therefore, even in the case of the method according to the invention, the reading out of the second item of information instead of the first item of information indicates a defective contact connection of the tested address line.
With the aid of the two methods according to the invention, it is possible to locate a defective solder contact (or bonding contact or contact established in some other way) by a customary memory access. As a result, neither unplanned electrical measurements nor optical examinations are required. The methods according to the invention are more reliable and less time-consuming than the conventional methods and also work in the case of memory modules with a number of memory chips, the pin contacts of which are connected in parallel via the address lines and are consequently short-circuited with respect to one another, since in the course of normal memory operation, which is used according to the invention, the control signals transmitted via the control lines ensure that a single memory chip is selectively accessed during writing or reading.
It is preferably provided that the series of steps a) to d) is carried out as often as corresponds to the number of address lines of the semiconductor chip, so that each address line is checked during precisely one instance of carrying out of the series of steps a) to d) for the functional capability of its electrical connection to an address line contact. In this way, the conducting connection of each address line to the respectively assigned address line contact is successively checked.
It is preferably provided that, whenever the check in step d) shows that the second item of information has been read out, an interruption of the electrical connection between that address line which has been electrically biased as the single address line and the assigned address line contact of the semiconductor memory chip is reported. If, in step c), the second item of information is read out, although step c) accesses the same memory address as step a), the first item of information written in step a) must have been overwritten by the second item of information, which is only possible if the electrical biasing has been blocked on account of a defective address line contact.
The first item of information is preferably a digital data bit and the second item of information is the digital data bit that is inverse to the first data bit. The first and second items of information are a digital xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, or vice versa.
A preferred embodiment provides that the address lines are operated by the multiplexing technique, in which the word line address and the bit line address of a memory address to be selected are selected one after the other by specific electrical biasing of the address lines. The memory addresses (cells) of a semiconductor chip are disposed in rows (bit lines) and columns (word lines). Their addresses are specified by two multi-digit binary numbers, denoted here as x and y. In the control of the semiconductor chip, each time a memory address is selected, first its bit line address and then its word line address is transmitted via the address lines, or vice versa. Therefore, those three memory addresses for which the address line to be checked is electrically biased only when transmitting the bit line address or only when transmitting the word line address or is electrically biased when transmitting both addresses can be used as the memory address of which the selection depends on the electrical biasing of precisely one address line.
It is preferably provided that that address line which is electrically biased as the single address line during the sequence of steps a) to d) is biased only when selecting bit line addresses. The electrical biasing has the effect that, in step b) in the first method according to the invention and in steps a) and c) in the second method, a memory address assigned to the biased bit line is accessed as long as the electrical connection is closed. In the case that a semiconductor memory has more bit lines than word lines, the bit line addresses are longer and, by contrast with the word lines, are transmitted by a relatively large number of address lines. If, in the case of this embodiment, the electrical biasing voltage is applied only during the selection of the bit line, more address lines can be checked than in the case of biasing when selecting word lines. Generally, electrical biasing is applied during selection of that address line type which has more address lines, e.g. the X-addresses. The X-addresses include all word line addresses plus the addresses for the memory banks.
With the method according to the invention, precisely one single address line is tested in each case. To test a number of address lines, and possibly all of them, a development of the invention provides that the sequence of steps a) to d) is repeated, a different address line being electrically biased with each repetition of the sequence.
Another development provides that a memory module which has a number of semiconductor chips on the printed circuit board, the address line contacts of which are connected in parallel by the address lines of the printed circuit board, is tested by a control signal being used to select a single semiconductor chip of which the memory addresses are exclusively accessed during steps a) to d). In this way it is possible to test one after the other a number of memory chips connected in parallel by the address lines, for which a resistance measurement fails on account of the short-circuited, parallel-connected pin contacts.
A development of the invention provides that electrical biasing voltages of the address lines are used to set an operating mode for checking the electrical connections which determines the type of data transmission between the printed circuit board and the semiconductor memory chip, the operating mode that is set being one which requires only a single address line to be electrically biased for its setting. If one or more address line contacts are interrupted, the semiconductor memory chip no longer functions properly, which is equivalent to total failure. The test mode used according to the invention, in which however selected memory addresses are specifically accessed, must first be set before the test can be carried out. This initialization also requires setting of the manner and methods by which data are to be transported into the memory addresses or taken from them. This setting also requires the activation, i.e. electrical biasing, of address lines. Since, however, some of these may be interrupted, it is advantageous to choose a manner of transmission which requires only a single address line to be biased for its setting.
It is preferably provided that the number of data bits transmitted one after the other per write command or read command, their sequence and/or the length of a delay time between the access to a word line during reading and the transmission of read data bits are set by the set operating mode in such a way that the same address line is biased for each setting. For example, what is known as the burst length is set to xe2x80x9c1xe2x80x9d and the sequence of data to be transmitted with a bus width of 4 bits is fixed as 1-2-3-4 (xe2x80x9csequential burst typexe2x80x9d). The xe2x80x9ccolumn address strobe latencyxe2x80x9d, which specifies the delay time between the opening of a word line and the reading out of an item of information from a specific bit line crossing the word line, is fixed, for example, at two clock units. All three settings merely require the biasing of the same address line, so that all the other address lines can be tested.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method of checking electrical connections between a memory module and a semiconductor memory chip, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.